1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2011-105186, filed May 10, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, the nanoscaling of semiconductor devices has been progressing. If the gate length of a transistor is made short, there is cased short-channel effect in the transistor, with the sub-threshold current increasing, and the transistor threshold voltage (Vt) decreasing.
In the case where the impurity concentration in the semiconductor substrate is increased to suppress the decrease of the transistor threshold voltage (Vt), the junction leakage current increases.
For this reason, in the case of nanoscaling of memory cells in a DRAM (dynamic random-access memory) used as the semiconductor device, deterioration of the refresh characteristics will be caused.
Japanese Patent Application Publication No. JPA 2006-339476 and Japanese Patent Application Publication No. JPA 2007-081095 disclose a so-called trench gate transistor (recessed-channel transistor), in which a gate electrode is buried in a trench formed in the front surface side of the semiconductor substrate and, making the transistors have the above-noted constitution, it is possible to physically and sufficiently achieve an effective channel length (gate length), thereby enabling a DRAM having nanoscaled cells with a minimum process dimension of 60 nm or smaller.
In Japanese Patent Application Publication No. JPA 2007-081095, there is disclosure of a DRAM having first and second gate trenches formed to be adjacent to one another in a p-type silicon substrate (semiconductor substrate) with a prescribed spacing therebetween, a gate insulating film formed on the inner wall surface of the first and second gate trenches, a first gate electrode that buries the first gate trench with a gate insulating film intervening therebetween and that also protrudes from the main surface of the p-type silicon substrate, a second gate electrode that buries the second gate trench with a gate insulating film intervening therebetween and that also protrudes from the main surface of the p-type silicon substrate, an impurity diffusion region formed in the p-type silicon substrate at a position between the first gate electrode and the second gate electrode and that will serve as a source/drain region common to the first and second gate electrodes, and an interlayer insulating film that is formed on the surface of the p-type silicon substrate and that also covers the part of the first and second gate electrodes that protrudes from the surface of the p-type silicon substrate.